This invention relates to a method for producing power semiconductor devices, and more particularly to insulated gate power device fabrication process and structure. More specifically, this application is directed to improvements in a single-mask process based on that disclosed in applicant's U.S. Pat. No. 4,895,810 to make four-layer(PNPN) devices, such as insulated gate transistors (IGT or IGBT), MOS controlled thyristors (MCT), emitter controlled thyristors and other gate controlled minority carrier devices, as well as power MOSFET devices.
U.S. Pat. No. 4,895,810 discloses a MOSFET fabrication process and structure which, among other advantages, substantially eliminates the incidence of fatal defects in a power device as a consequence of defects in, and/or misalignment between, the layers used in the production of such devices. This process uses a single mask to form all of the active device areas of a MOSFET structure, with recessed source regions self-aligned to an MOS gate structure and sized by sidewall spacers and an enhanced-conductivity body region underlying and self-aligned to the source regions.
Based on teachings available in the prior art, it was believed that the previously-disclosed MOSFET fabrication process and structure could be readily adapted to the fabrication of insulated gate bipolar transistors and other gate-controlled four-layer devices. That proved to be much more difficult than was thought.
The development of insulated gate bipolar transistors and other gate-controlled four-layer (PNPN) devices can be traced through the following references:
Atalla U.S. Pat. No. 3,206,670 PA1 New U.S. Pat. No. 3,210,563 PA1 Gentry, U.S. Pat. No. 3,324,359 PA1 Plummer, U.S. Pat. No. 4,199,774 PA1 Becke et al, U.S. Pat. No. 4,364,075 PA1 Temple, U.S. Pat. No. 4,417,385 PA1 Baliga U.S. Pat. No. 4,443,931 PA1 Baliga, Power Junction Gate Field Controlled Devices, IEDM pp. 76-78, 1979 PA1 Plummer et al, Insulated Gate Planar Thyristors: PA1 Leipold et al, A FET-Controlled Thyristor in SIPMOS Technology, IEDM pp. 79-82, 1980 PA1 Tihanyi, Functional Integration of Power MOS and Bipolar Devices, IEEE pp. 75-78, 1980 PA1 Baliga et al, The Insulated Gate Rectifier (IGR): PA1 Russell et al., The Comfet-A New High Conductance MO Gated Device, IEEE Electron Device Lett., EDL-4, pp. 63, 1983 PA1 Wheatley et al, COMFET--The Ultimate Power Device; A General Study of Power Devices, Solid State Technology pp. 121-128, November 1985 PA1 Kuo et al., Modeling The Turn-off Characteristics of the Bipolar-MOS Transistor, IEEE Electron Device Lett., EDL-6, pp. 211-214, 1985 PA1 Kuo and Hu, Optimization of Epitaxial Layers for Power Bipolar-MOS Transistor, IEEE Electron Device Lett., EDL-7, p. 510-512, 1986 PA1 Lorenz, Selection Criteria for Power Semiconductor for Motor Drives, Proceedings of 1990 International Symposium on Power Semiconductor Devices and ICs, Tokyo, pp. 263-269, 1990 PA1 Tsunoda et al., Improved 600- and 1200V-IGBT with Low Turn-off Loss and High Ruggedness, Proceedings of the Power Electronics Specialists Conference, San Antonio, Tex., pp. 9-16, June 1990 PA1 Baliga, MODERN POWER DEVICES, Ch. 7 and 8, 1987
Ohmi, Power Static Induction Transistor Technology, IEDM pp. 84-87 (See FIG. 7), 1979
I--Structure and Basic Operation PA2 II--Quantitative Modeling IEEE Trans. Electron Devices, ED--27 pp. 380-394, 1980 PA2 A New Power Switching Device, IEDM pp. 264-267, 1982
With knowledge of this art, applicant tried to make insulated gate bipolar transistors based on applicant's prior work and experience and could not fabricate commercially operative devices. Such devices exhibited latchup under virtually all operating conditions, even when using a buffered N+ layer as taught by Becke et al. and analyzed by A. Nakagawa et al of Toshiba in "Non-Latchup 1200V 75A Bipolar-Mode MOSFET with Large ASO" IEDM, pp. 860-861, 1984, and "Experimental and Numerical Study of Non-Latch-up Bipolar Mode MOSFET Characteristics" IEDM, pp. 150-153, 1985.
Not only was latchup obtained under different conditions in applicant's experimental devices, latchup occurred in different cells and regions of the devices. Problems were particularly acute when trying to switch an inductive load. Current turnoff time also proved to be very slow &gt;1 .mu.S. At the same time, it remains important to maintain both a low forward voltage drop or on-resistance, and to have sufficient reverse blocking capability. Also, such devices require an adequate ability to withstand high voltage(V.sub.ce) short circuit conditions.
The performance requirements for IBGTs today has advanced substantially from where they were in the mid 1980's. More parameters are being evaluated for device selection such as discussed by Lorenz. The early analyses by Kuo and Nakagawa were optimizing for forward voltage drop and switching speed without considerations for ruggedness such as short circuit withstand capability and safe operating area (SOA). Given the more stringent requirements of the 1990's, the recommendations of these early works are no longer completely valid. For example, the optimal epi design-suggested by Kuo and Hu of &gt;5 .mu.m thick N+ layer at 10.sup.18 /cm.sup.3 doping level operating with N- layer completely depleted would be a terribly weak device on short circuit withstand capability even though the forward voltage may be good.
A. Nakagawa et al (IEDM 85) describe the need for PNP common base current gain .alpha.&gt;0.27 to maintain sufficient conductivity modulation hence a low forward voltage drop using an N+ buffer layer under an N-drift region. No consideration was given to designing for ruggedness by epitaxial material selection. Device ruggedness is directly impacted by the high voltage/high current gain. We have discovered that this characteristic is affected by the N+ thickness and doping concentration. A. Nakagawa et al do not describe these aspects of their device although they and others have used about 3.times.10.sup.16 -10.sup.18 /cm.sup.3 doping concentrations in their analyses and discussions and less than about 20 micrometers thickness for the N+ buffer layer. Tsunoda et al. reported experiments with adjusting the N-layer thickness and the N+ doping profile, but nothing in regard to N+ layer thickness. The paper did not give any values on layer thicknesses or doping concentrations for the devices measured and analyzed.
Siemens has, conversely, proposed elimination of the N+ layer altogether and, instead, making the N-layer very thick, e.g., 200-350 micrometers, without minority carrier lifetime control, as described by T. Laska in "A 2000 V-Non-Punch-Through-IGBT with Dynamical Properties like a 1000 V-IGBT" IEDM, pp. 807-810, 1990. The main drawback of this long-base approach is very high forward voltage or conduction loss (high on-resistance). Petterteig and Rogne compared switching losses of various vendor's samples of IGBT-type devices including applicant's initial experimental devices, in EPE FIRENZE, 1991, and showed that, in hard turnoff condition, the long-base Siemens device does not completely switch off after a few microseconds compared to less than about one microsecond for the other devices.
Other latching countermeasures are known to have been tried in the prior art but with varied success and questionable applicability to the particular process, using a single mask and recessed source contact areas, employed by applicant to fabricate devices. Goodman et al. U.S. Pat. No. 4,587,713 uses a deeply implanted laterally-extending supplemental P+ doped region in the P-type base to reduce bipolar transistor gain. Blanchard U.S. Pat. No. 4,345,265 employs a distributed diode with lower breakdown voltage than the DMOS transistor to non-destructively absorb transients and a shunt conductance for the channel region to reduce both voltage and voltage gradient in the base. Yilmaz U.S. Pat. No. 4,809,045 provides paths for reverse current flow spaced from the emitter-base junction and enlarges the ratios of the base region and the emitter region surface areas in contact with the emitter electrode within a contact window. Nakagawa et al disclose, in UK Pat. Application No. 2,161,649A, various methods for avoiding latchup by keeping the saturation current of the device smaller than the latch-up current, including proportioning of active device areas and providing a hole-current path from the drain to the source.
Prior workers have also tried different ways to control minority carrier lifetimes within the device. Baliga, MODERN POWER DEVICES, pp. 36-58, 380-387 and 410-413, describes how the switching speed of the IGT, P-i-N rectifiers and other devices can be increased by the introduction of recombination centers in the N-base region to reduce minority carrier lifetime. In general, two approaches have been used, either diffusion of transition elements impurities such as gold or platinum into the silicon or by high energy particle bombardment, e.g., by neutron, proton, electron or gamma irradiation, to create lattice damage in the silicon. Among these approaches, Baliga teaches that electron irradiation is preferred, offering among various advantages tighter distribution in device characteristics. U.S. Pat. No. 3,953,243 issued to Goetzberger et al. teaches ion implantation and diffusion of gold plantinum into a semiconductor substrate with pn junctions until change carrier lifetime is approximately stationary. Using lifetime control involves tradeoffs in device operation, as discussed in Temple et al., "Optimizing Carrier Lifetime Profile for Improved Tradeoff Between Turn-Off Time and Forward Drop," IEEE Transactions on Electron Devices, Vol. ED-30, No. 7, pp 782-790, July 1983.
Conventionally, diffusion of transition elements impurities is performed for lifetime control purposes by deposition of a 100 .ANG. to 1000 .ANG. thick layer of the selected element onto a surface of the silicon wafer and diffusing atoms of the element from the layer into the silicon at a temperature in the range of 800.degree.-900.degree. C. The diffusion temperature determines the solid solubility of the impurity atoms in silicon and can be used to control the impurity density. Metal implantation has also been used for other purposes. For example, high dose implants have been used to create ohmic contacts in integrated circuits. Low dose implantation (up to 2.times.10.sup.13 /cm.sup.2) has been used to adjust Schottky barrier height in discrete devices and integrated circuits. In these procedures, the dose is retained near the surface.
The particle bombardment approach uses either electron, proton, neutron or gamma irradiation. It is typically performed at room temperature, and then the devices are subjected to a low-temperature annealing procedure, although Baliga states that high temperature (300.degree. C.) electron radiation has been used.
Several drawbacks exist, however, in these approaches to lifetime control. Both approaches, as practiced in the prior art, can substantially increase leakage current. The particle bombardment approach also causes threshold instability. Low temperature annealing is typically required to restore the desired threshold voltage by partially annihilating trapped charge in the gate oxide and at the gate oxide-silicon interface. Once the devices have been irradiated and annealed, however, they cannot be subjected to higher temperatures in further fabrication procedures, such as during die attachment. The devices are also subject to long-term instability during use in high temperature applications. Radiation defects anneal out between 300.degree. C. and 400.degree. C. This is a temperature range necessary to achieve good wetting of silicon to package during die attachment.
Evaporation and diffusion of transition metal impurities into silicon is not subject to such instability effects but, as conventionally practiced, is difficult to control. It also creates the largest increase in leakage current compared to similarly processed devices without lifetime control. For example, conventional diffusion of platinum from a layer evaporatively deposited onto the silicon surface yields an increased leakage current that is one to two orders of magnitude higher than the leakage current produced by irradiation and particle bombardment, and three orders of magnitude higher than no lifetime control. Alternatively, a technique for spinning on a layer of platinum (e.g., Emulsitone platinum film) is commonly used (See Lisiak et al, J. Appl. Phys. Vol. 46, No. 12, pg. 5229, December 1975). This procedure also provides poor dosage control. Thus, a better lifetime control method is needed.
It has been previously observed and is the subject of applicant's co-pending U.S. patent application Ser. No. 07/663,297, SEMICONDUCTOR DEVICE WITH DOPED ELECTRICAL BREAKDOWN CONTROL REGION (continuation of Ser. No. 06/842,464, filed Mar. 21, 1986), that there are regions on a device layout that are prone to lower breakdown voltage than otherwise achievable from the active cells which tend to be of similar repetitive dimensions. These breakdown-prone regions are typically created out of necessity, for example, to provide gate bonding pads and low signal-delay buses. In order to retain the performance capability inherent in the cells while permitting proper interfacing and signal propagation on a chip, application Ser. No. 07/663,297 disclosed doping under these structures with the same dopant type as the body diffusion with well-matched junction depth to smooth out the transition from the body to diffusion under the gate so as to form a single contiguous region of smooth curvature. The base resistance of the parasitic bipolar transistor is reduced much below that of the active cells due to the pad/routing bus doping into the body regions. The net effect is the total elimination of premature breakdown and failure during inductive switching at gate pads/gate routing buses below the designed capability of the active cells. The active MOS channels around the periphery of the odd gate structures are also rendered completely inactive by so doing. Thus, a better way is needed to suppress breakdown under gate bus areas in large current MOSFET and IGBT-type devices without substantially reducing useful channel.
After a semiconductor device is processed and metallized, a passivation or scratch protection layer is typically deposited on the top surface. Only the bonding pads are opened to make electrical connections outside the chip after this step. This passivation layer must be a moisture and mobile ion barrier against the harsh environment that is hazardous to MOS devices in the packaging and assembly area. This goal is met in low voltage devices by using a silicon nitride-based film or a PSG (phosposilicate glass) film (&lt;4%). The most popular methods in use today for film deposition are PECVD (Plasma Enhanced Chemical Vapor Deposition) and LTO (Low Temperature Oxide)deposition. PECVD can be used to deposit both nitride and oxide while the latter method (LTO) is used only for oxide. Both methods work very well for passivating low voltage semiconductor devices. When these same quality films are conventionally deposited on top of high voltage devices, however, undesirable polarization effect develops which is not observable at low voltage.
Polarization effect per se is known to the integrated circuits industry where it is not a serious problem but it is not at all well understood for high voltage applications. In a prior art disclosure (U.S. Pat. No. 4,399,449, column 8, lines 19-2), the inventors clearly specify the removal of a polarizable film of heavily doped silox (phosphorus content must exceed 6%, typically 8% is used, to have substantial reflow of the deposited silicon oxide film) in the guard ring area of a high voltage device. No details are disclosed as to the limits of the film property or the mechanism of the problem. The literature has been fairly silent on similar effects on lower doping PSG and silicon nitride films even though the problem of polarization has been recognized on other types of films such as borosilicate glass (Murakami et al., "Polarization Induced Instability in a Glass Passivated p-n Junction" J. Electrochem. Soc., Vol. 133, No. 7, pp. 1467-1471, July 1986. Stress, composition, and wet etching characteristics have been reported previously such as by Claassen et. al. (Characterization of Silicon-Oxynitride Films Deposited by Plasma-Enhanced CVD, ibid, pp. 1458-1463) for oxynitride films deposited with varying gas phase compositions. Barrier effectiveness of oxynitride has also been the subject of studies such as by Hashimoto et al. (Properties of PEVD SiOxNy Films as Selective Diffusion Barrier, ibid, pp. 1464-1467) for Zn. However, no information on polarizability has been disclosed on these films. Thus, further development of passivation films is needed for high voltage power switching devices.
Accordingly, a need remains for an IGBT-type power device structure and fabrication process that can produce high voltage solid-state power switches capable of conducting and switching high currents and voltages at high speed but without undesirable parasitic effects.